Silicon large-scale integrated circuits, among other device technologies, are increasing in use in order to provide support for the advanced information society of the future. An integrated circuit can be composed of a plurality of semiconductor devices, such as transistors or the like, which can be produced according to a variety of techniques. To continuously increase integration and speed of semiconductor devices, a trend of continuously scaling semiconductors (e.g., reducing size and features of semiconductor devices) has emerged. Reducing semiconductor and/or semiconductor feature size provides improved speed, performance, density, cost per unit, etc., of resultant integrated circuits. However, as semiconductor devices and device features have become smaller, conventional fabrication techniques have been limited in their ability to produce finely defined features.
Conventionally, front-end-of-line (FEOL) fabrication processing of an integrated circuit relates to patterning of devices (e.g., transistors, capacitors, resistors, etc.) in the semiconductor. Formation of interconnects to facilitate connection of the various devices conventionally occurs during back-end-of-line (BEOL) fabrication. By way of example, interconnects are formed during BEOL fabrication of an integrated circuit structure to facilitate connection between conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines comprising an integrated circuit structure. A particular aspect in interconnect formation is a via, where a via can be formed in an insulator, dielectric, or similar structure, and facilitates connection between the various conductive elements comprising the integrated circuit structure.
Single damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, the conductive via openings also are formed. In conventional dual damascene processing, the insulating layer is coated with a resist material which is exposed to a first mask including the image pattern of the via openings, and the pattern is anisotropically etched in the upper half of the insulating layer. After removal of the patterned resist material, the insulating layer is coated with a resist material which is exposed to a second mask with the image pattern of the conductive lines in alignment with the via openings. By anisotropically etching the openings for the conductive lines in the upper half of the insulating material, the via openings already present in the upper half are simultaneously etched in the lower half of the insulating material. After the etching is complete, both the vias and grooves are filled with metal.
Conventionally, by utilizing a dual damascene process, semiconductor devices can be patterned with several thousand openings for conductive lines, interconnects, and vias, which are filled with a conductive metal, such as aluminum or copper, and serve to interconnect the active and/or passive elements of the integrated circuit. The dual damascene process is also used for forming the multilevel signal lines of conductive metal in the insulating layers of multilayer substrate on which semiconductor devices are mounted.
Owing to miniaturization of the semiconductor devices and, accordingly, the conductive elements (e.g., a metal line) located therein, creation of an interconnect(s) in a multilayer semiconductor stack has become an exacting process, pushing the limits of ability for contemporary photolithographic techniques to form an interconnect(s) having the correct dimensions (e.g., critical dimensions) and location in relation to the conductor with which the interconnect is to interface.
As shown in FIG. 20, a plurality of issues relate to the formation of a via having the required critical dimensions and location relative to a conductor, metal line 2010. Via V1 has been formed with a desired critical dimension d, where in this particular example the diameter d of via V1 is less than width W of metal line 2010, and via V1 is aligned correctly with regard to the centerline CL and width W of metal line 2010. V1a V2 has been formed such that via V2 is misaligned with respect to the centerline CL of metal line 2010. As shown, the junction between via V2 and metal line 2010 is not 100%, with a portion of via V2 overhanging metal line 2010, resulting in a contact having detrimental properties compared with via V1, for example via V2 has inferior electrical properties (e.g., inferior current flow) compared with via V1. Via V3 depicts an issue where a current technology, e.g., photolithography, is unable to produce a via having the desired dimension(s) (e.g., critical dimension) with regard to the width W of metal line 2010. Hence, the diameter D of via V3 is greater than width W of metal line 2010, and such an oversize structure can lead to issues such as leakage currents (e.g., tunneling), parasitic capacitance, and the like, with other proximate conductive elements and components. Hence, dimensional control of the via is critical. Accordingly, it would be desirable to form one or more via's correctly aligned with regard to an element (e.g., a metal line) comprising an integrated circuit structure and the via is formed with desired critical dimension(s).